Difference between revisions of "Communication Protocols"
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(Added protocol files) |
(Documenting change in PHCC2host protocol (analog all axes dump) in firmware 0.1.8) |
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* [[DOB bus|Digital Output Type B]] bus (using a two-wire syncronous serial interface). | * [[DOB bus|Digital Output Type B]] bus (using a two-wire syncronous serial interface). | ||
* I<sup>2</sup>C bus. | * I<sup>2</sup>C bus. | ||
| + | |||
The PHCC system and the host PC have their own protocol stacked on top of the RS-232 bus. | The PHCC system and the host PC have their own protocol stacked on top of the RS-232 bus. | ||
Details of this protocol can be found in the following documents: | Details of this protocol can be found in the following documents: | ||
| − | * [ | + | * Host to PHCC: [[Media:Host2PHCC_Protocol.xfig.pdf]] |
| − | * [ | + | * PHCC to Host: [[Media:PHCC2HostProtocol.xfig.pdf]] |
| + | ** The analog all axes dump differ from specification in firmware 0.1.8. The first packet sent by the motherboard only contain the packet type (b10100000). The next packet contains the upper 2 bits from the 10 bits ADC. The following byte contains the rest of the 8 bits from the ADC. These two packet are repeated for each analog input. The ''all-bits-one-byte'' and "all-bits-zero-byte" finally close the transmission. For more information, consult line 899 from [[Media:Firmware18.asm]]. | ||
Latest revision as of 22:10, 2 June 2011
PHCC Communication Interfaces, Busses, and Protocols
The following communication protocols are used in the PHCC system:
- RS-232 (between PHCC motherboard and the host PC).
- Digital Output Type A bus (using the AP2PP protocol).
- Digital Output Type B bus (using a two-wire syncronous serial interface).
- I2C bus.
The PHCC system and the host PC have their own protocol stacked on top of the RS-232 bus.
Details of this protocol can be found in the following documents:
- Host to PHCC: Media:Host2PHCC_Protocol.xfig.pdf
- PHCC to Host: Media:PHCC2HostProtocol.xfig.pdf
- The analog all axes dump differ from specification in firmware 0.1.8. The first packet sent by the motherboard only contain the packet type (b10100000). The next packet contains the upper 2 bits from the 10 bits ADC. The following byte contains the rest of the 8 bits from the ADC. These two packet are repeated for each analog input. The all-bits-one-byte and "all-bits-zero-byte" finally close the transmission. For more information, consult line 899 from Media:Firmware18.asm.